Home > Intel i960

The i960 design started as a re-implementation of Intel's failed i432 design of the early 1980s. The i432 was very powerful, but terribly slow. However these two issues were not related, the poor performance was the result of CPU design, not the powerful instructions it included. In the mid-1980s Intel and Siemens started a joint project to create the BiiN machine, and as a part of this project the i432 was re-built on a RISC core, creating the 960 MC.

Although the 960 MC was never released commercially, Intel later took the core processor design, dropped the i432 instructions and complex microcode, and was left with a simple but powerful RISC CPU. Early versions were full CPU designs with an MMU, but this competed head-to-head with their i860 design which was promoted as "the" Intel RISC system, and so the i960 was re-targeted at the embedded market, losing the MMU.

The i960 was designed from the start to be used in superscalar designs, with the instructions being dispatched to one or more integer ALUs. The first implementations of the chip only included one ALU, but modern versions with multiple ALUs were available in 1989. There are sixteen 32-bit global registers, and sixteen register "caches" for fast routine calls (similar to the register windowIn computer engineering, the use of register windows is a technique to improve the performance of a particularly common operation, the procedure call. By devoting hardware to this problem, almost all computer programs will run faster. This was one of thes concept pioneered in the Berkeley RISC design). Unlike most Intel designs, the i960 has a flat 32-bit memory space, with no memory segmentationSegmented memory is a methodology employed by computer programmers. It is the practice of dividing working memory into blocks. The segments are created initially, but generally can be adjusted in size or number at a later time if needed (different operati.

External Links

• i960 homepage at Intel
• i960 images and descriptions at cpu-collection.de