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The POWER design is descended directly from the earlier IBM 801 CPU, widely considered to be the first true RISC chip design. It was used in a number of applications inside IBM hardware, but did not become public until they released the poorly-performing IBM PC/RT in the mid-1980s.
At about the same time the PC/RT was being released, IBM started the America Project, to design the most powerful CPU on the market. They were interested primarily in fixing two problems in the 801 design in the resulting POWER design:
Floating point became a focus for the America Project, and IBM were able to use new algorithms developed in the early 1980s that could support 64-bit double-precision multiplies and divides in a single cycle. The FPU portion of the design was separate from the instruction decoder and integer parts, allowing the decoder to send instructions to both the FPU and ALU (integer) execution units at the same time. IBM complemented this with a complex instruction decoder which could be fetching one instruction, decoding another, and sending one to the ALU and FPU at the same time, resulting in one of the first superscalar CPU designs in use.
The system used thirty-two 32-bit integer registers and another thirty-two 64-bit floating point registers, each in their own unit. The branch unit also included a number of "private" registers for its own use, including the program counter.
The 801 was a simple design, and an overcorrection to its simplicity resulted in the POWER design being more complex than most RISC CPUs. For instance, the POWER (and PowerPC) instruction setAn instruction set or instruction set architecture (ISA), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception han includes over 100 op-codes of variable length, many of which are variations on others. This compares (for instance) with the ARMCambridge The Acorn RISC Machine (or ARM is a RISC processor architecture that is widely used in a number of applications. It is a very "pure" RISC implementation, and is considered one of the most elegant modern processors. History The ARM design was sta which has only 34 instructions.
Another interesting feature of the architecture is a virtual address system which maps all addresses into a 52-bit space. In this way applications can share memory in a "flat" 32-bit space, and all of the programs can have different blocks of 32-bits each.
The first POWER1 CPUs consisted of three chips; branch, integer and floating point. These were wired together on a largish motherboard to produce a single system. POWER1 was used primarily in the RS/6000The IBM pSeries formerly called RS/6000 (for R ISC S ystem 6000 , is IBM's current RISC/ UNIX-based workstation computer line. Announced in 1990, the RS/6000 replaced the RT-PC. It is based on the IBM POWER CPU architecture and runs the AIX operating syst series of workstations.
POWER2 was a product-improved POWER1 and was the longest-lived of the POWER series, released in 1993 and still in use five years later. It added a second floating-point unit, 256k of cache and 128-bit floating point math.
POWER3 followed in 1998, moving to a full 64-bit implementation, while remaining completely compatible with the POWER instruction set. This had been one of the goals of the PowerPC project and the POWER3 was the first of the IBM processors to take advantage of it. It also added a third ALU and a second instruction decoder, for a total of eight functional units.
The POWER4 series which places two complete CPU cores (otherwise similar to the POWER3) on a single chip, speeds it up, and adds high-speed connections to up to three other pairs of POWER4 CPUs. They can be placed together on a motherboard to produce an 8-CPU SMPSMP is a Three letter abbreviation which can refer to the following: In computing: Symmetric multiprocessing, the use of multiple CPUs. In the context of Unicode, the Supplementary Multilingual Plane (Plane One). Suomen Maaseudun Puolue ( Finnish Rural Pa building block. When processing requires high throughput instead of high code complexity, one of a pair of cores can be turned off so that the remaining cores have the entire bus and L3 cache to themselves. The POWER4, even in single form, is considered by many to be the most powerful CPU available. In 2003, IBM introduced a single CPU core version of the POWER4 called the 970. It was employed in the newest generation of AppleApple Computer, Inc. is a Silicon Valley company based in Cupertino, California, whose main business is computer technologies. Best known for its range of Macintosh computers and, more recently, its iPod personal audio ( MP3 and otherwise) player and iTun desktop computers (i.e., the G5).
IBM rolled out the POWER5 processor in 2004. The processor the 1.9Ghz version posted the highest uniprocessor SpecFP score of any shipping chip.
Ravi Arimilli, IBM's chief microprocessor designer has said; "The Power5 chip is more of a midrange or low-end design that can drive up to the high end and then down to things like blades.". Improvements in the POWER5 over the POWER4 include: a larger L2 cache, a memory controller on the chip, simultaneous multithreadingSimultaneous multithreading often referred to as SMT is a relatively recent technology to improve the performance of superscalar processors. Normal multithreading operating systems allow multiple processes and threads to utilize the processor one at a tim (similar to the " Hyperthreading" feature in the newer versions of Pentium 4), and power-saving features. A 64-bit RISC design that will help IBM cover the entire board as far as high and low end server CPUs are being announced by Intel and AMD. This is no low-end chip however, and is slated to slowly phase out the POWER4.