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The CDC 6600 was designed by Seymour Cray at his Chippewa Falls, WI lab. CDC's first products were based on the machines designed at ERA, which Cray had been asked to update. Cray wanted to return to his home town and "bluesky" the next generation of machines, and CDC's CEO, William Norris agreed and set him up in his own lab in 1957, with the understanding that Cray would be allowed to develop their next machine as he saw fit. Starting around 1960, his goal was to create the fastest machine in the world. With sales of their other machines doing well, Control Data allowed Cray as much time as he liked to build his next design.

The basis for the 6600 is what we would today refer to as a RISC system, one in which the processor is tuned to do instructions which are comparatively simple. The philosophy of many other machines was toward using instructions which were complicated — for example, a single instruction which would fetch an operand from memory and add it to a value in a register. In the 6600, loading the value from memory would require one instruction, and adding it would require a second. The reason for this "limitation" was to simplify timing within the CPU, allowing it to keep several instructions flowing through the processor in an instruction pipeline, leading to higher throughput and a higher clock speed, 100ns.

The Central Processor, or CU, has eight general purpose 60- bit registers X0 through X7, eight 18-bit address registers A0 through A7, and eight 18-bit scratchpad registers B0 through B7 (typically used for array indexing). Additional registers used for bookkeeping (such as the scoreboard register) are not accessible to the programmer. Additional registers (such as RA and FL) can be loaded only by the operating system.

In keeping with the RISC "load/store" philosophy, there are no instructions to read or write from/to core memory. All memory accesses are performed through loading an address into the A registers, loading A1 through A5 with an address would cause the data word at that location to be read into the corresponding X register (X1 through X5), while loading an address into A6 or A7 would cause register X6 or X7 to be written out to memory at that address. In modern designs this sort of operation is normally supported directly by load/store instructions, which include their own hardware to handle such operations.

User programs are restricted to use only a portion of contiguous core memory. The portion of memory the program has access to is controlled by the RA (Relative Address) and FL (Field Length) registers, and when a user program tries to read or write a word in central memory at address a, the processor will first check that a is between 0 and FL-1. If this passes, the processor will access the word in central memory at address RA+a. This process is known as logical address translation ; each user program sees core memory as a contiguous block of FL words starting at address 0, while in fact the program may be anywhere in the physical memory.

Using this technique, each user program can be moved around in core memory by the operating system, as long as the RA register reflects its position in memory. A user program trying to access memory outside the allowed range will trigger an error, and will be terminated by the operating system. When this happens, a core dumpA core dump is a file containing the contents of memory at the time a program or computer crashed. It can be loaded into a debugger to get some idea of what the program was trying to do when it crashed. In the early days of computing, computer memory was will be output in a file, allowing the developer a way to know what happened.

However, contrary to virtual memoryVirtual memory is a computer design feature that permits software to use more memory than the computer physically possesses. In technical terms, it allows software to run in a memory address space whose size and addressing are not necessarily tied to the systems, the entirety of a process addressable space must be in core memory. Support for virtual memory came with later CDC CyberThe Control Data Corporation Cyber is a range of supercomputers manufactured during the 1970's and 1980's, based on the architecture of the CDC 6600 and CDC 7600. Primarily aimed at large office applications instead of the traditional supercomputer tasks, 180 models.

To handle the 'household' tasks which other designs put in the CPU, Cray included in the 6600 ten other processors, based partly on his earlier computer, the CDC 160 A. These machines, called Peripheral Processors, or PPs, were full computers in their own right, but were tuned to performing I/O tasks and running the operating system. When the main CPU needed to perform some sort of I/O, it instead loaded a small program into one of these other machines and let it do the work. The PP would then inform the CPU when the task was complete with an interrupt.

The central processor had 60-bit words, whilst the peripheral processors had 12-bit words. CDC used the term "byte" to refer to 12-bit entities used by peripheral processors; characters were 6-bit, and central processor instructions were either 15 bits, or 30 bits with an 18-bit address field, the latter allowing for a directly addressable memory space of 256K words (converted to modern terms, with 8-bit bytes, this is 1.88 megabytes). Central processor instructions started on a word boundary when they were the target of a jump statement or subroutine return jump instruction, so no-operations were sometimes required to fill out the last 15, 30 or 45 bits of a word.

The 6-bit characters could be used to store up to 10 characters in a word. This permitted a character set of 64 characters. This is enough for all upper case letters, digits, and some punctuation. Certainly, enough to write FORTRAN, or print financial or scientific reports. There were actually two character sets in use, 64-character and 63-character. The 64-character set had the disadvantage that two consecutive ':' (colon) characters might be interpreted as the end of a line if they fell at the end of a 10-byte word.

With no byte addressing instructions at all, code had to be written to pack and shift characters into words. The very large words, and comparatively small amount of memory, meant that programmers would frequently enonomise on memory by packing data into words at the bit level.